DALLAS DS1WM

as more 1-wire devices become available, more and more users have to deal with the demands of generating 1-wire signals to communicate to them. this usually requires "bit-banging" a port pin on a microprocessor, and having the microprocessor perform the timing functions required for the 1-wire protocol. while 1-wire transmission can be interrupted mid-byte, it cannot be interrupted during the "low" time of a bit time slot; this means that a cpu will be idled for up to 60 microseconds for each bit sent and at least 480 microseconds when generating a 1-wire reset. the 1-wire master helps users handle communication to 1-wire devices in their system without tying up valuable cpu cycles. integrated into a users asic as a 1-wire port, the verilog or vhdl core uses little chip area (3470 gates plus 2 bond pads). this circuit is designed to be memory mapped into the users system and provides complete control of the 1-wire bus through 8-bit or single commands. the host cpu loads commands, reads and writes data, and sets interrupt control through six individual registers. all of the timing and control of the 1-wire bus are generated within. the host merely needs to load a command or data and then may go on about its business. when bus activity has generated a response that the cpu needs to receive, the 1-wire master sets a status bit and, if enabled, generates an interrupt to the cpu. in addition to write and read simplification, the 1-wire master also provides a search rom accelerator function relieving the cpu from having to perform the complex single-bit operations on the 1-wire bus.