Cypress Semiconductor Corp CY2309CZXI-1T

Description
The CY2305C and CY2309C are 3.3 V zero delay buffers designed to distribute high-speed clocks. They are available in 16-pin SOIC or TSSOP packages (CY2309C) and an 8-pin SOIC package (CY2305C). The devices accept one reference input and drive out multiple low-skew clocks. The CY2309C has two banks of four outputs each, while the CY2305C has five outputs.
The CY2305C and CY2309C have on-chip phase-locked loops (PLLs) that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The PLLs enter a power-down mode when there are no rising edges on the REF input, resulting in low current draw.
The CY2309C has a test mode to bypass the PLL, allowing the REF input to be directly output to the outputs. This mode is useful for chip and system testing purposes.

Features
10 MHz to 100-133 MHz operating range
Zero input and output propagation delay
Multiple low-skew outputs
One input drives five outputs (CY2305C)
One input drives nine outputs, grouped as 4 4 1 (CY2309C)
50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Test mode to bypass phase-locked loop (PLL) (CY2309C) only
Available in space-saving 16-pin 150 Mil SOIC or 4.4 mm thin TSSOP packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C)
3.3 V operation
Commercial, industrial, and automotive-A flows available

Applications
Clock distribution
High-speed data transmission
Test and measurement equipment
Networking equipment
Telecommunications equipment