IDT, Integrated Device Technology Inc CSPUA877ABVG8
- Part Number:
- CSPUA877ABVG8
- Manufacturer:
- IDT, Integrated Device Technology Inc
- Ventron No:
- 2983704-CSPUA877ABVG8
- Description:
- IC PLL CLK DVR SDRAM 52-CABGA
- Datasheet:
- CSPUA877ABVG8
Description
The CSPUA877A is a PLL-based clock driver that distributes one differential clock input pair (CLK, CLK) to 10 differential output pairs (Y[0.9], Y(0.9)) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) are provided for synchronization of the outputs to the input reference. OE, OS, and Avoo control the power-down and test mode logic. When Avon is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, the device enters a low power-down mode, disabling receivers, turning off the PLL, and disabling output clock drivers, resulting in a current consumption of less than 500μA.
Features
1 to 10 differential clock distribution
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications
Operating frequency: 125MHz to 410MHz
Stabilization time: <6us
Very low skew: $40ps
Very low jitter: $40ps
1.8V AVDD and 1.8V VoDQ
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 52-Ball VFBGA and 40-pin VFQFPN packages
Applications
Meets or exceeds JEDEC standard CUA877 for registered DDR2 clock driver
Along with SSTUA32864/66, DDR2 register, provides a complete solution for DDR2 DIMMS
The CSPUA877A is a PLL-based clock driver that distributes one differential clock input pair (CLK, CLK) to 10 differential output pairs (Y[0.9], Y(0.9)) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) are provided for synchronization of the outputs to the input reference. OE, OS, and Avoo control the power-down and test mode logic. When Avon is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, the device enters a low power-down mode, disabling receivers, turning off the PLL, and disabling output clock drivers, resulting in a current consumption of less than 500μA.
Features
1 to 10 differential clock distribution
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications
Operating frequency: 125MHz to 410MHz
Stabilization time: <6us
Very low skew: $40ps
Very low jitter: $40ps
1.8V AVDD and 1.8V VoDQ
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 52-Ball VFBGA and 40-pin VFQFPN packages
Applications
Meets or exceeds JEDEC standard CUA877 for registered DDR2 clock driver
Along with SSTUA32864/66, DDR2 register, provides a complete solution for DDR2 DIMMS
IDT, Integrated Device Technology Inc CSPUA877ABVG8 technical specifications, attributes, parameters and parts with similar specifications to IDT, Integrated Device Technology Inc CSPUA877ABVG8.
- Factory Lead Time7 Weeks
- Mounting TypeSurface Mount
- Package / Case52-VFBGA
- Operating Temperature0°C~70°C
- PackagingTape & Reel (TR)
- Part StatusActive
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Voltage - Supply1.7V~1.9V
- Base Part NumberIDTCSPUA877
- Number of Circuits1
- Frequency (Max)410MHz
- InputClock
- Ratio - Input:Output1:10
- PLLYes
- Differential - Input:OutputYes/Yes
- Main PurposeMemory, DDR2, SDRAM
- RoHS StatusROHS3 Compliant
The three parts on the right have similar specifications to CSPUA877ABVG8.
-
ImagePart NumberManufacturerFactory Lead TimeMounting TypePackage / CaseOperating TemperaturePackagingPart StatusMoisture Sensitivity Level (MSL)Voltage - SupplyBase Part NumberNumber of CircuitsFrequency (Max)InputRatio - Input:OutputPLLDifferential - Input:OutputMain PurposeRoHS StatusContact PlatingMountNumber of PinsPublishedJESD-609 CodePbfree CodeNumber of TerminationsECCN CodeTerminal FinishMax Operating TemperatureMin Operating TemperatureTerminal PositionTerminal FormPeak Reflow Temperature (Cel)Number of FunctionsSupply VoltageTerminal PitchReflow Temperature-Max (s)Pin CountQualification StatusOperating Supply VoltageTemperature GradeFamilyMax I(ol)Same Edge Skew-Max (tskwd)Number of True OutputsLengthWidthThicknessLead FreeSupplier Device PackageOutputView Compare
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CSPUA877ABVG87 WeeksSurface Mount52-VFBGA0°C~70°CTape & Reel (TR)Active3 (168 Hours)1.7V~1.9VIDTCSPUA8771410MHzClock1:10YesYes/YesMemory, DDR2, SDRAMROHS3 Compliant---------------------------------
-
----Tape & Reel (TR)Discontinued3--1340MHzClock-Yes--RoHS CompliantCopper, Silver, TinSurface Mount522002e1yes52EAR99Tin/Silver/Copper (Sn/Ag/Cu)70°C0°CBOTTOMBALL26011.8V0.65mm3052Not Qualified1.8VCOMMERCIAL8770.009 A0.04 ns107mm4.5mm1mmLead Free--
-
-Surface Mount56-VFBGA0°C~70°CTape & Reel (TR)Obsolete3 (168 Hours)1.7V~1.9VIDTCSPU8771340MHzClock1:10YesYes/YesMemory, DDR2, SDRAM-------------------------------56-CABGA (4.5x7.0)Clock
-
12 WeeksSurface Mount40-VFQFN Exposed Pad0°C~70°CTrayActive3 (168 Hours)1.7V~1.9VIDTCSPUA8771410MHzClock1:10YesYes/YesMemory, DDR2, SDRAMROHS3 Compliant--------------------------------
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