Texas Instruments CDCM1804RGERG4

Description
The CDCM1804 is a clock driver that distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs (Y[2:0] and Y[2:0]) and one LVCMOS singleended output (Y3). It is designed for clock distribution applications and features low output skew (15 ps typical for LVPECL outputs) and a programmable output divider for two LVPECL outputs and the LVCMOS output. The CDCM1804 also provides a VBB bias voltage output for singleended input signals.

Features
Distributes one differential clock input to three LVPECL differential clock outputs and one LVCMOS singleended output
Programmable output divider for two LVPECL outputs and LVCMOS output
Low output skew (15 ps typical) for LVPECL outputs
1.6ns output skew between LVCMOS and LVPECL transitions
Vec range: 3 V3.6 V
Differential input stage for wide commonmode range
Receiver input threshold: ±75 mV
24terminal QFN package (4 mm x 4 mm)
Accepts any differential signaling: LVDS, HSTL, CML, VML, SSTL2
Accepts singleended signaling: LVTTL/LVCMOS

Applications
Clock distribution
Data communication
Networking
Test and measurement