Texas Instruments CDC960

200-MHz Clock Synthesizer/Driver with Spread Spectrum & Device Control Interface
The CDC960 is a clock synthesizer/driver and buffer that generates CPU, PCI, PCI/LDT, USB, FDC, and REF system clock signals to support PCs with an AMD-K8 Clawhammer-class system. All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided at the XIN input instead of a crystal. It is recommended to use the bypass mode of the internal oscillator in this case. Two phase-locked loops (PLLs) are used to generate the host frequencies and 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external components. The device provides a standard mode (100 kbps) SMBus 1.1 serial interface for device control. The implementation is as a slave with read and write capability. The device address is specified in the SMBus serial interface device address table. Both SMBus inputs (SDATA and SCLK) provide integrated pullup resistors (typically 150 k). Seven 8-bit SMBus registers provide individual enable control for each of the outputs. The controllable outputs default to enabled at power up and can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers not supported). The CPU, PCI, PCI_F, LDT, FDC (24/48-MHz), and USB (48-MHz) clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs FS0, FS1, and FS2 at power-up preset condition. The CPU bus is a 3.3-V differential push-pull output type. All others are single-ended CMOS buffers. The host frequencies are fixed and are controlled by the FS0, FS1 and FS2 signals at power-up. The CPU bus frequencies are 200, 166, 133 and 100 MHz. Because the CDC960 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. With use of external reference clock, this signal must be fixed-frequency and fixed-phase prior stabilization time starts.