Texas Instruments CDC3RL02BYFPR

Description
The CDC3RL02 is a twochannel clock fanout buffer designed for portable devices requiring minimal additive phase noise and fanout capabilities. It buffers a single master clock to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enables a single clock output.
The CDC3RL02 accepts square or sine waves at the master clock input (MCLK IN), eliminating the need for an AC coupling capacitor. It has been designed to offer minimal channeltochannel skew, additive output jitter, and additive phase noise. The adaptive clock output buffers offer controlled slewrate over a wide capacitive loading range, minimizing EMI emissions, maintaining signal integrity, and minimizing ringing caused by signal reflections on the clock distribution lines.
The CDC3RL02 has an integrated LowDropOut (LDO) voltage regulator that accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8V supply is externally available to provide regulated power to peripheral devices such as a TCXO.
The CDC3RL02 is offered in a 0.4mm pitch waferlevel chipscale (WCSP) package (0.8 mm x 1.6 mm) and is optimized for very low standby current consumption.

Features
Low Additive Noise:
149 dBc/Hz at 10kHz Offset Phase Noise
0.37 ps (RMS) Output Jitter
Limited Output Slew Rate for EMI Reduction (1 to 5ns Rise/Fall Time for 10pF to 50pF Loads)
Adaptive Output Stage Controls Reflection
Regulated 1.8V Externally Available I/O Supply
UltraSmall 8bump YFP 0.4mm Pitch WCSP (0.8 mm x 1.6 mm)
ESD Performance Exceeds JESD 222000V HumanBody Model (A114A)
1000V ChargedDevice Model (JESD22C101A Level III)

Applications
Cellular Phones
Global Positioning Systems (GPS)
Wireless LAN
FM Radio
WiMAX
WBT