IDT, Integrated Device Technology Inc 9DBV0241AKILFT

Description
The 9DBV0241 is a member of Renesas' 1.8V Very-Low-Power (VLP) PCle family. It is a 2-output, 1.8V PCle Zero Delay/Fanout Clock Buffer with Zo = 100 ohms.

Features
Two 1-200MHz Low-Power (LP) HCSL DIF pairs with Zo=1000
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
PCle Gen5 CC additive phase jitter < 40fs RMS
12kHz-20MHz additive phase jitter = 156fs RMS at 156.25MHz (typical)
LP-HCSL outputs with Zo = 1000; saves 8 resistors compared to standard HCSL outputs
35mW typical power consumption in PLL mode; reduced thermal concerns
Spread Spectrum (SS) compatible; allows use of SS for EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by common clock sources
SMBus-selectable features; optimize signal integrity to application
Selectable slew rate for each output
Selectable differential output amplitude
Pin/software selectable PLL bandwidth and PLL Bypass; optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not required for device control
3.3V tolerant SMBus interface; works with legacy controllers
Space saving 4 x 4mm 24-VFQFPN; minimal board space

Applications
1.8V PCle Gen1-5 Zero-Delay/Fan-out Buffer (ZDB/FOB)