IDT, Integrated Device Technology Inc 852S41AYLF
- Part Number:
- 852S41AYLF
- Manufacturer:
- IDT, Integrated Device Technology Inc
- Ventron No:
- 3771346-852S41AYLF
- Description:
- IC SWITCH RIO
- Datasheet:
- 852S41AYLF
Description
The ICS853017 is a quad 1-to-1, 2.5V/3.3V/5V differential LVPECL/ECL receiver and a member of the Hiperclocks family of High Performance Clock Solutions from IDT. The ICS853017 operates with a positive or negative power supply at 2.5V, 3.3V or 5V, and can accept both single-ended and differential inputs. For single-ended operation, an internally generated voltage, which is available on output pin Ve can be used as a switching bias voltage on the unused input of the differential pair. V can also be used to rebias AC coupled inputs.
Features
Four differential LVPECL / ECL 1:1 receivers
Four differential LVPECL clock input pairs
Dx, nDx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
Output frequency: >2GHz (typical)
Translates any single ended input signal to LVPECL levels with resistor bias on nDx input
Output skew: TBD
Part-to-part skew: TBD
Propagation delay: 320ps (typical)
LVPECL mode operating voltage supply range: Vcc -2.375V to 5.25V
ECL mode operating voltage supply range: Voc-OV. V -5.25V to -2.375V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
Not Recommended for New Design
Applications
High-speed clock distribution
Clock and data recovery
Level translation
Signal conditioning
The ICS853017 is a quad 1-to-1, 2.5V/3.3V/5V differential LVPECL/ECL receiver and a member of the Hiperclocks family of High Performance Clock Solutions from IDT. The ICS853017 operates with a positive or negative power supply at 2.5V, 3.3V or 5V, and can accept both single-ended and differential inputs. For single-ended operation, an internally generated voltage, which is available on output pin Ve can be used as a switching bias voltage on the unused input of the differential pair. V can also be used to rebias AC coupled inputs.
Features
Four differential LVPECL / ECL 1:1 receivers
Four differential LVPECL clock input pairs
Dx, nDx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
Output frequency: >2GHz (typical)
Translates any single ended input signal to LVPECL levels with resistor bias on nDx input
Output skew: TBD
Part-to-part skew: TBD
Propagation delay: 320ps (typical)
LVPECL mode operating voltage supply range: Vcc -2.375V to 5.25V
ECL mode operating voltage supply range: Voc-OV. V -5.25V to -2.375V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
Not Recommended for New Design
Applications
High-speed clock distribution
Clock and data recovery
Level translation
Signal conditioning
IDT, Integrated Device Technology Inc 852S41AYLF technical specifications, attributes, parameters and parts with similar specifications to IDT, Integrated Device Technology Inc 852S41AYLF.
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)3 (168 Hours)
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