74LVX273M

Fairchild/ON Semiconductor 74LVX273M

Part Number:
74LVX273M
Manufacturer:
Fairchild/ON Semiconductor
Ventron No:
3209255-74LVX273M
Description:
IC D-TYPE POS TRG SNGL 20SOIC
ECAD Model:
Datasheet:
74LVX273M

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Specifications
Fairchild/ON Semiconductor 74LVX273M technical specifications, attributes, parameters and parts with similar specifications to Fairchild/ON Semiconductor 74LVX273M.
  • Factory Lead Time
    6 Weeks
  • Lifecycle Status
    ACTIVE (Last Updated: 2 days ago)
  • Contact Plating
    Tin
  • Mount
    Surface Mount
  • Mounting Type
    Surface Mount
  • Package / Case
    20-SOIC (0.295, 7.50mm Width)
  • Number of Pins
    20
  • Weight
    801mg
  • Operating Temperature
    -40°C~85°C TA
  • Packaging
    Tube
  • Series
    74LVX
  • JESD-609 Code
    e3
  • Pbfree Code
    yes
  • Part Status
    Active
  • Moisture Sensitivity Level (MSL)
    1 (Unlimited)
  • Number of Terminations
    20
  • ECCN Code
    EAR99
  • Subcategory
    FF/Latches
  • Technology
    CMOS
  • Voltage - Supply
    2V~3.6V
  • Terminal Position
    DUAL
  • Terminal Form
    GULL WING
  • Supply Voltage
    2.7V
  • Base Part Number
    74LVX273
  • Function
    Master Reset
  • Output Type
    Non-Inverted
  • Operating Supply Voltage
    2.5V
  • Number of Elements
    1
  • Polarity
    Non-Inverting
  • Supply Voltage-Min (Vsup)
    2V
  • Number of Channels
    8
  • Load Capacitance
    50pF
  • Number of Bits
    8
  • Clock Frequency
    90MHz
  • Propagation Delay
    20 ns
  • Quiescent Current
    4μA
  • Turn On Delay Time
    7.1 ns
  • Family
    LV/LV-A/LVX/H
  • Logic Function
    D-Type, Flip-Flop
  • Current - Output High, Low
    4mA 4mA
  • Max I(ol)
    0.004 A
  • Max Propagation Delay @ V, Max CL
    14.5ns @ 3.3V, 50pF
  • Trigger Type
    Positive Edge
  • Input Capacitance
    4pF
  • Number of Input Lines
    3
  • Clock Edge Trigger Type
    Positive Edge
  • Height
    2.34mm
  • Length
    12.8mm
  • Width
    7.47mm
  • Radiation Hardening
    No
  • RoHS Status
    ROHS3 Compliant
  • Lead Free
    Lead Free
Description
74LVX273M Overview
The package or case of the device is a 20-SOIC, with a width of 0.295 inches or 7.50mm. The ECCN code for this device is EAR99, indicating that it does not have any specific export control requirements. The supply voltage required for this device is 2.7V. The function of the device is to act as a master reset. The output type is non-inverted, meaning that the output signal is the complement of the input signal. The minimum supply voltage required for proper operation is 2V. This device has a total of 8 channels. The load capacitance for this device is 50pF. The propagation delay, or the time it takes for the output to respond to a change in the input, is 20 ns. The quiescent current, or the current consumed by the device when it is not actively switching, is 4μA.

74LVX273M Features
Tube package
74LVX series
20 pins
8 Bits

74LVX273M Applications
There are a lot of ON Semiconductor 74LVX273M Flip Flops applications.

Test & Measurement
CMOS Process
ESD performance
ESD protection
ESCC
QML qualified product
Single Down Count-Control Line
Memory
Power down protection
Computing
74LVX273M More Descriptions
Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin SOIC W Rail
74LVX, SMD, 74LVX273, SOIC20; Logic IC function:Octal D-Type Flip-Flop with Reset; Positive-Edge Trigger; Logic IC family:LVX; Logic IC Base Number:74273; Case style:SOIC; Temperature, operating range:-40°C to 85°C; Base number:74; Gates, No. of:8; IC Generic number:74LVX273; Inputs, No. of:1; Logic function number:273; Pins, No. of:20; Temp, op. max:85°C; Temp, op. min:-40°C; Termination Type:SMD; Voltage, supply:3.6V; Voltage, supply max:3.6V; Voltage, supply min:2.7V
The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.
Certification
  • ISO 9001
  • ISO 13485
  • ISO 45001
  • ASA
  • ESD
  • DUNS
  • SMTA
  • ROHS

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