Texas Instruments 74ALVCH16820DLG4
- Part Number:
- 74ALVCH16820DLG4
- Manufacturer:
- Texas Instruments
- Ventron No:
- 3707784-74ALVCH16820DLG4
- Description:
- IC D-TYPE POS TRG SNGL 56SSOP
- ECAD Model:
-
- Datasheet:
- SN74ALVCH16820
Texas Instruments 74ALVCH16820DLG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments 74ALVCH16820DLG4.
- MountSurface Mount
- Mounting TypeSurface Mount
- Package / Case56-BSSOP (0.295, 7.50mm Width)
- Number of Pins56
- Operating Temperature-40°C~85°C TA
- PackagingTube
- Series74ALVCH
- JESD-609 Codee4
- Pbfree Codeyes
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Number of Terminations56
- Terminal FinishNickel/Palladium/Gold (Ni/Pd/Au)
- TechnologyCMOS
- Voltage - Supply1.65V~3.6V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)260
- Supply Voltage1.8V
- Reach Compliance Codeunknown
- Reflow Temperature-Max (s)NOT SPECIFIED
- Base Part Number74ALVCH16820
- FunctionStandard
- Qualification StatusNot Qualified
- Output TypeTri-State, Non-Inverted
- Number of Elements1
- PolarityNon-Inverting
- Number of Circuits2
- Number of Ports2
- Clock Frequency150MHz
- Propagation Delay5.5 ns
- Turn On Delay Time1 ns
- FamilyALVC/VCX/A
- Logic FunctionD-Type, Flip-Flop
- Current - Quiescent (Iq)40μA
- Current - Output High, Low24mA 24mA
- Number of Bits per Element10
- Max Propagation Delay @ V, Max CL4.8ns @ 3.3V, 50pF
- Trigger TypePositive Edge
- Input Capacitance3.5pF
- Number of Output Lines3
- Clock Edge Trigger TypePositive Edge
- Width7.49mm
- RoHS StatusROHS3 Compliant
74ALVCH16820DLG4 Overview
This product features a surface mount design and can be mounted on a surface. It has an operating temperature range of -40°C to 85°C TA. The terminal finish is Nickel/Palladium/Gold (Ni/Pd/Au) and the terminal position is DUAL. It has a peak reflow temperature of 260°C and operates at a supply voltage of 1.8V. This product has 2 circuits and a positive edge clock edge trigger type. It has a width of 7.49mm.
74ALVCH16820DLG4 Features
Tube package
74ALVCH series
56 pins
74ALVCH16820DLG4 Applications
There are a lot of Texas Instruments 74ALVCH16820DLG4 Flip Flops applications.
Latch-up performance
Consumer
Matched Rise and Fall
Registers
2 – Bit synchronous counter
Memory
Safety Clamp
EMI reduction circuitry
Functionally equivalent to the MC10/100EL29
Computers
This product features a surface mount design and can be mounted on a surface. It has an operating temperature range of -40°C to 85°C TA. The terminal finish is Nickel/Palladium/Gold (Ni/Pd/Au) and the terminal position is DUAL. It has a peak reflow temperature of 260°C and operates at a supply voltage of 1.8V. This product has 2 circuits and a positive edge clock edge trigger type. It has a width of 7.49mm.
74ALVCH16820DLG4 Features
Tube package
74ALVCH series
56 pins
74ALVCH16820DLG4 Applications
There are a lot of Texas Instruments 74ALVCH16820DLG4 Flip Flops applications.
Latch-up performance
Consumer
Matched Rise and Fall
Registers
2 – Bit synchronous counter
Memory
Safety Clamp
EMI reduction circuitry
Functionally equivalent to the MC10/100EL29
Computers
74ALVCH16820DLG4 More Descriptions
10-BIT TO 20-BIT D-TYPE FLIP-FLOPIC FF D-TYPE SNGL 10BIT 56SSOP
This 10-bit flip-flop is designed for 1.65-V to 3.6-V VCC operation. The flip-flops of the SN74ALVCH16820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or undriven inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 10-bit flip-flop is designed for 1.65-V to 3.6-V VCC operation. The flip-flops of the SN74ALVCH16820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or undriven inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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