Texas Instruments 74ABTH18504APMRG4
- Part Number:
- 74ABTH18504APMRG4
- Manufacturer:
- Texas Instruments
- Ventron No:
- 3226591-74ABTH18504APMRG4
- Description:
- IC SCAN TEST UNIV TXRX 64LQFP
- Datasheet:
- SN54ABTH18(2)504A, SN74ABTH18(2)504A
Texas Instruments 74ABTH18504APMRG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments 74ABTH18504APMRG4.
- MountSurface Mount
- Mounting TypeSurface Mount
- Package / Case64-LQFP
- Number of Pins64
- Operating Temperature-40°C~85°C
- PackagingTape & Reel (TR)
- Series74ABTH
- Pbfree Codeyes
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations64
- HTS Code8542.39.00.01
- Packing MethodTRAY
- TechnologyBICMOS
- Voltage - Supply4.5V~5.5V
- Terminal PositionQUAD
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)NOT SPECIFIED
- Number of Functions1
- Supply Voltage5V
- Terminal Pitch0.5mm
- Reflow Temperature-Max (s)NOT SPECIFIED
- Base Part Number74ABTH18504
- Pin Count64
- Qualification StatusNot Qualified
- Supply Voltage-Max (Vsup)5.5V
- Power Supplies5V
- Supply Voltage-Min (Vsup)4.5V
- Number of Circuits20-Bit
- Number of Ports2
- Number of Bits20
- FamilyABT
- Logic FunctionTransceiver
- Output Characteristics3-STATE
- Current - Output High, Low32mA 64mA
- Logic TypeScan Test Universal Bus Transceiver
- Output PolarityTRUE
- Propagation Delay (tpd)5.5 ns
- Control TypeINDEPENDENT CONTROL
- Power Supply Current-Max (ICC)27mA
- Count DirectionBIDIRECTIONAL
- TranslationN/A
- Height Seated (Max)1.6mm
- Length10mm
- Width10mm
- RoHS StatusROHS3 Compliant
74ABTH18504APMRG4 Overview
As part of 64-LQFP, it is embedded. It is packaged in the way of Tape & Reel (TR). In order to achieve this superior flexibility, 20-Bit circuits are used. A Scan Test Universal Bus Transceiver is the logic type of the electrical device that we are discussing. A Surface Mount-shaped electronic component is mounted here. A higher operating temperature than -40°C~85°C is recommended. In addition, 32mA 64mA features the highest level of flexibility in its design due to its high and low output currents. It is a type of FPGA that belongs to the 74ABTH series of FPGAs. It operates at a voltage of 4.5V~5.5V. It belongs to 74ABTH18504 family. In 64 terminations, a transmission line is terminated with an impedance-matched device. It is recommended that the supply voltage be kept above 5V for normal operation. 64 pins are included. It is designed with 20 Bits. There are a number of termination types, including 2 terminations, which is the term that refers to the practice of terminating a transmission line with a device that matches the characteristic impedance of the line. In this case, the electronic part will be mounted in the Surface Mount-direction. 64 pins are used in the design of this board. This electronic device belongs to the family of ABT. At this point, Vsup reaches its maximum value. It is recommended that the supply voltage (Vsup) be greater than 4.5V. The power source is 5V. The device's reliability makes it well suited for TRAY.
74ABTH18504APMRG4 Features
64-LQFP package
74ABTH series
74ABTH18504 family
64 pin count
64 pins
5V power supplies
74ABTH18504APMRG4 Applications
There are a lot of Texas Instruments 74ABTH18504APMRG4 Universal Bus Functions applications.
Instrumentation Systems
Fishery-optical complementary power station
Sewing machine
Microcontrollers
Data transfer
Memory
Solar street light
Automatic watering system
Island protection
Burglar alarms and buzzers
As part of 64-LQFP, it is embedded. It is packaged in the way of Tape & Reel (TR). In order to achieve this superior flexibility, 20-Bit circuits are used. A Scan Test Universal Bus Transceiver is the logic type of the electrical device that we are discussing. A Surface Mount-shaped electronic component is mounted here. A higher operating temperature than -40°C~85°C is recommended. In addition, 32mA 64mA features the highest level of flexibility in its design due to its high and low output currents. It is a type of FPGA that belongs to the 74ABTH series of FPGAs. It operates at a voltage of 4.5V~5.5V. It belongs to 74ABTH18504 family. In 64 terminations, a transmission line is terminated with an impedance-matched device. It is recommended that the supply voltage be kept above 5V for normal operation. 64 pins are included. It is designed with 20 Bits. There are a number of termination types, including 2 terminations, which is the term that refers to the practice of terminating a transmission line with a device that matches the characteristic impedance of the line. In this case, the electronic part will be mounted in the Surface Mount-direction. 64 pins are used in the design of this board. This electronic device belongs to the family of ABT. At this point, Vsup reaches its maximum value. It is recommended that the supply voltage (Vsup) be greater than 4.5V. The power source is 5V. The device's reliability makes it well suited for TRAY.
74ABTH18504APMRG4 Features
64-LQFP package
74ABTH series
74ABTH18504 family
64 pin count
64 pins
5V power supplies
74ABTH18504APMRG4 Applications
There are a lot of Texas Instruments 74ABTH18504APMRG4 Universal Bus Functions applications.
Instrumentation Systems
Fishery-optical complementary power station
Sewing machine
Microcontrollers
Data transfer
Memory
Solar street light
Automatic watering system
Island protection
Burglar alarms and buzzers
74ABTH18504APMRG4 More Descriptions
IC SCAN TEST UNIV TXRX 64LQFP
Contact for details
The 'ABTH18504A and 'ABTH182504A scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM universal bus transceivers. Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), clock-enable ( and ), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and is low, A-bus data is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active. When is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the , LEBA, , and CLKBA inputs. In the test mode, the normal operation of the SCOPETM universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The B-port outputs of 'ABTH182504A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot. The SN54ABTH18504A and SN54ABTH182504A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH18504A and SN74ABTH182504A are characterized for operation from -40°C to 85°C. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKENBA, and CLKBA. Output level before the indicated steady-state input conditions were established
Contact for details
The 'ABTH18504A and 'ABTH182504A scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM universal bus transceivers. Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), clock-enable ( and ), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and is low, A-bus data is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active. When is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the , LEBA, , and CLKBA inputs. In the test mode, the normal operation of the SCOPETM universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The B-port outputs of 'ABTH182504A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot. The SN54ABTH18504A and SN54ABTH182504A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH18504A and SN74ABTH182504A are characterized for operation from -40°C to 85°C. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKENBA, and CLKBA. Output level before the indicated steady-state input conditions were established
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