IDT, Integrated Device Technology Inc 2305-1PGG8

Description
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer designed for high-speed clock distribution applications. It operates within a frequency range of 10 to 133MHz and features zero input-output delay, output skew less than 250ps, and low jitter less than 200ps cycle-to-cycle. The IDT2305 accepts one reference input and drives out five low skew clocks. It has an on-chip PLL that locks to the input clock on the REF pin and obtains feedback from the CLKOUT pad. In the absence of an input clock, the IDT2305 enters power down mode, drawing less than 25μA, tri-stating the outputs, and stopping the PLL.

Features
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
3.3V ZERO DELAY CLOCK BUFFER
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
IDT2305-1 for Standard Drive
IDT2305-1H for High Drive
No external RC network required
Operates at 3.3V VDD
Power down mode
Available in SOIC/TSSOP packages

Applications
High-speed clock distribution
Clock buffering
Zero delay clock distribution
Low skew clock distribution
Low jitter clock distribution