Texas Instruments SN74ALVC16835DLR

Name: SN74ALVC16835DLR
Brand: Texas Instruments
SKU: 3716828-SN74ALVC16835DLR
Availability: InStock
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Part Number:: SN74ALVC16835DLR

Manufacturer:: Texas Instruments

Ventron No:: 3716828-SN74ALVC16835DLR

Description:: IC UNIV BUS DVR 18BIT 56SSOP

ECAD Model:

Datasheet:: SN74ALVC16835DLR

Specifications

Texas Instruments SN74ALVC16835DLR technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74ALVC16835DLR.

Mount
Surface Mount
Mounting Type
Surface Mount
Package / Case
56-BSSOP (0.295, 7.50mm Width)
Number of Pins
56
Operating Temperature
-40°C~85°C
Packaging
Tape & Reel (TR)
Series
74ALVC
Pbfree Code
yes
Part Status
Obsolete
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
56
HTS Code
8542.39.00.01
Subcategory
Bus Driver/Transceivers
Packing Method
TAPE AND REEL
Technology
CMOS
Voltage - Supply
1.65V~3.6V
Terminal Position
DUAL
Terminal Form
GULL WING
Peak Reflow Temperature (Cel)
NOT SPECIFIED
Number of Functions
1
Supply Voltage
1.8V
Terminal Pitch
0.635mm
Reflow Temperature-Max (s)
NOT SPECIFIED
Base Part Number
74ALVC16835
Pin Count
56
Qualification Status
Not Qualified
Polarity
Non-Inverting
Supply Voltage-Max (Vsup)
3.6V
Power Supplies
3.3V
Supply Voltage-Min (Vsup)
1.65V
Number of Circuits
18-Bit
Load Capacitance
50pF
Number of Ports
2
Number of Bits
18
Propagation Delay
5.2 ns
Family
ALVC/VCX/A
Output Characteristics
3-STATE
Current - Output High, Low
24mA 24mA
Logic Type
Universal Bus Driver
Max I(ol)
0.024 A
Control Type
ENABLE LOW
Height Seated (Max)
2.79mm
Length
18.415mm
Width
7.49mm
RoHS Status
ROHS3 Compliant

Description

SN74ALVC16835DLR Overview
As part of the 56-BSSOP (0.295, 7.50mm Width) package, it is embedded. It is packaged in the way of Tape & Reel (TR). In order to achieve the high level of flexibility that it possesses, 18-Bit circuits are used. This electrical device is of the Universal Bus Driver logic type. There is an electronic part that is mounted in a Surface Mount-shaped arrangement. It is recommended that the operating temperature be higher than -40°C~85°C. High/Low output currents allow 24mA 24mA to have a maximum design flexibility. This is a type of FPGA from the 74ALVC series. Powered by 1.65V~3.6V, it operates on a voltage of V. 74ALVC16835 family is the family in which it belongs. In 56 terminations, a transmission line is terminated with an impedance-matched device. In order to function normally, the supply voltage should be higher than 1.8V. It is equipped with 56 pin count. This electronic part is designed with 18 Bits. Transmission lines are terminated with 2 terminations, which are devices matching the line's characteristic impedance. As you can see from the image, this electronic component is mounted in a Surface Mount-direction. The 56 pins are designed to be a part of it. This electronic device belongs to the family of ALVC/VCX/A. 3.6V is the maximum supply voltage (Vsup). The supply voltage (Vsup) should be greater than 1.65V. Power is provided by 3.3V power supplies. The reliable performance of this device makes it a good choice for TAPE AND REEL. This part is included in Bus Driver/Transceivers.

SN74ALVC16835DLR Features
56-BSSOP (0.295, 7.50mm Width) package
74ALVC series
74ALVC16835 family
56 pin count
56 pins
3.3V power supplies

SN74ALVC16835DLR Applications
There are a lot of Texas Instruments SN74ALVC16835DLR Universal Bus Functions applications.

MPPT function (maximum power point tracking)
Memory devices
Communication
In-vehicle system
Pocket PC
Audio
Overcurrent/Short circuit protection
Circuits involving computation and processing
Fax machine
Electronic Points of Sale

SN74ALVC16835DLR More Descriptions

IC UNIV BUS DVR 18BIT 56SSOP
Contact for details
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Certification