Silicon Labs SL2305SC-1T

Description
The SL2305 is a low skew, low jitter, and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for highspeed clock distribution applications. The product has an onchip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin.
The SL2305 is available with two (2) drive strength versions. The 1 is the standarddrive version and 1H is the highdrive version. The SL2305 highdrive version operates up to 140 MHz and the standard drive version 1 operates up to 100 MHz.
The SL2305 enters into PowerDown (PD) mode if the input at CLKIN is DC (0 to VDD). In this powerdown state, all five (5) outputs are tristated and the PLL is turned off, leading to less than 12 μAmax of power supply current draw.

Features
10 to 140 MHz operating frequency range
Low output clock jitter: 140 psmax ccj at 66 MHz
Low outputtooutput skew: 150 psmax
Low producttoproduct skew: 400 psmax
3.3 V power supply range
Low power dissipation:
14 mAmax at 66 MHz
26 mAmax at 133 MHz
One input drives 5 outputs organized as 4 1
Spread Thru™ PLL that allows use of SSCG
Standard and HighDrive options
Available in 8pin SOIC and TSSOP packages
Available in Commercial and Industrial grades

Applications
Printers and MFPs
Digital Copiers
PCs and Work Stations
DTV
Routers, Switchers, and Servers
Digital Embedded Systems