Silicon Labs SI53115-A01AGM

Description
The Si53115 is a 15output, lowpower HCSL differential clock buffer that meets all the performance requirements of the Intel DB1200ZL specification.
The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCle Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications.
The VCO of the device is optimized to support 100 MHz and 133 MHz operation.
Each differential output can be enabled through I2C for maximum flexibility and power savings.

Features
Fifteen 0.7 V lowpower, pushpull HCSL PCle Gen3 outputs
100 MHz /133 MHz PLL operation, supports PCle and QPI
PLL bandwidth SW SMBUS programming overrides the latch value from HW pin
9 selectable SMBUS addresses
SMBus address configurable to allow multiple buffers in a single control network
3.3 V supply voltage operation
Separate VDDIO for outputs
PLL or bypass mode
Spread spectrum tolerable
1.05 to 3.3 V I/O supply voltage
50 ps outputtooutput skew
50 ps cyccyc jitter (PLL mode)
Low phase jitter (Intel® QPI, PCle Gen 1/Gen 2/Gen 3 compliant)
100 ps inputtooutput delay
Extended Temperature: 40 to 85 °C
64pin QFN

Applications
Server
Storage
Data center
Enterprise switches and routers