Texas Instruments SA555D

Description
Precision timing circuits capable of producing accurate time delays or oscillation.
Time-delay (mono-stable) mode: Timed interval controlled by external resistor and capacitor network.
A-stable mode: Frequency and duty cycle controlled independently by two external resistors and a single external capacitor.
Threshold and trigger levels typically two-thirds and one-third of Vcc, respectively.
Control-voltage terminal allows adjustment of these levels.
Flip-flop set when trigger input falls below trigger level, output goes high.
Flip-flop reset when trigger input above trigger level and threshold input above threshold level, output goes low.
Reset input overrides all other inputs, initiates new timing cycle.
Low-impedance path between discharge (DISCH) and ground when output is low.
Output circuit can sink or source up to 200 mA.
Operation specified for supplies of 5 V to 15 V.
TTL-compatible output levels with 5-V supply.

Features
Timing from microseconds to hours.
Astable or monostable operation.
Adjustable duty cycle.
TTL-compatible output.
Can sink or source up to 200 mA.

Applications
Fingerprint biometrics.
Iris biometrics.
RFID readers.