ON Semiconductor MC10H642FN

Description
The MC10H/100H642 generates the necessary clocks for the 68030, 68040, and similar microprocessors. It meets the clock specifications required by the 68030 and 68040 in terms of parttopart skew, withinpart skew, and duty cycle skew. The user can choose to use either TTL or PECL (ECL referenced to 5.0 V) for the input clock. The H642 also uses differential PECL internally to achieve its superior skew characteristic.
The H642 includes dividebytwo and dividebyfour stages to achieve the necessary duty cycle skew and generate MPU clocks as required. A typical 50 MHz processor application would use an input clock running at 100 MHz, thus obtaining output clocks at 50 MHz and 25 MHz.
The 10H version is compatible with MECL 10H™ ECL logic levels, while the 100H version is compatible with 100K levels (referenced to 5.0 V).

Features
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single 5.0 V Supply
PbFree Packages are Available

Applications
Clock Generation for 68030/040 Microprocessors
HighSpeed Clock Distribution
ECLtoTTL Clock Conversion