ON Semiconductor MC10EP195FAG

Description
The MC10/100EP195 is a Programmable Delay Chip (PDC) designed for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers. The delay increment has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real-time delay values by D[9:01. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D[10:0].
Select input pins D[10:0] may be threshold controlled by combinations of interconnects between VEF (pin 7) and VCF (pin 8) for LVCMOS, ECL, or LVTTL level signals. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs.

Features
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range: Vcc 3.0 V to 3.6 V with VER=0 V
NECL Mode Operating Range: Vcc 0 V with VEE= -3.0 V to -3.6 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic Low
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
VBB Output Reference Voltage
Pb-Free Packages are Available

Applications
Clock Deskewing
Timing Adjustment
Signal Delay