Texas Instruments LMK04208NKDR

Description
The LMK04208 is a high-performance clock conditioner with superior clock jitter cleaning, generation, and distribution capabilities. It features a dual-loop PLLatinum™ architecture that enables ultra-low RMS jitter performance of 111 fs (12 kHz to 20 MHz) when paired with a low-noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) with an external crystal and varactor diode.
The dual-loop architecture consists of two high-performance phase-locked loops (PLLs), a low-noise crystal oscillator circuit, and a high-performance voltage-controlled oscillator (VCO). PLL1 provides low-noise jitter cleaner functionality, while PLL2 performs clock generation. PLL1 can be configured to work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a narrow loop bandwidth, PLL1 utilizes the superior close-in phase noise of the VCXO module or tunable crystal to clean the input clock. The output of PLL1 serves as the clean input reference for PLL2, which locks the integrated VCO. PLL2's loop bandwidth can be optimized to clean the far-out phase noise where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

Features
Ultra-low RMS jitter performance:
111 fs, RMS jitter (12 kHz to 20 MHz)
123 fs, RMS jitter (100 Hz to 20 MHz)
Dual-loop PLLatinum™ PLL architecture
Integrated low-noise crystal oscillator circuit
Holdover mode when input clocks are lost
Automatic or manual triggering/recovery
PLL2-normalized PLL noise floor of -227 dBc/Hz
Phase detector rate of up to 155 MHz
OSCin frequency-doubler
Integrated low-noise VCO or external VCO mode
Two redundant input clocks with LOS-automatic and manual switch-over modes
50% duty cycle output divides, 1 to 1045 (even and odd)
6 LVPECL, LVDS, or LVCMOS programmable outputs
Digital delay: fixed or dynamically adjustable 25 ps step
Analog delay control
7 differential outputs
Up to 14 single-ended outputs
Up to 6 VCXO/crystal buffered outputs
Clock rates of up to 1536 MHz
0-delay mode
Three default clock outputs at power up
Multi-mode: dual PLL, single PLL, and clock distribution
Industrial temperature range: -40°C to 85°C
3.15-V to 3.45-V operation
64-pin WQFN package (9.0 x 9.0 x 0.8 mm)

Applications
Clock distribution
Data converter clocking
Wireless infrastructure
Networking, SONET/SDH, DSLAM
Medical, video, military, aerospace
Test and measurement