Lattice Semiconductor Corporation ISPPAC-CLK5320S-01TN64C

Description
The ispClock5300S family is a high-performance, in-system programmable, zero-delay universal fan-out buffer with single-ended outputs. It offers exceptional power supply noise immunity and is available in commercial (0 to 70°C) and industrial (-40 to 85°C) temperature ranges.

Features
Four operating configurations:
Zero delay buffer
Zero delay and non-zero delay buffer
Dual non-zero delay buffer
Non-zero delay buffer with output divider
8MHz to 267MHz input/output operation
Low output to output skew (<100ps)
Low jitter peak-to-peak (<70 ps)
Up to 20 programmable fan-out buffers with programmable single-ended output standards and individual enable controls (LVTTL, LVCMOS, HSTL, eHSTL, SSTL)
Programmable output impedance (40 to 700Ω in 52 increments)
Programmable slew rate
Up to 10 banks with individual Vcco and GND (1.5V, 1.8V, 2.5V, 3.3V)
Fully integrated high-performance PLL with programmable lock detect, three "Power of 2" output dividers (5-bit), programmable on-chip loop filter, compatibility with spread spectrum clocks, and internal/external feedback
Precision programmable phase adjustment (skew) per output (8 settings; minimum step size 156ps) locked to VCO frequency
Up to /- 5ns skew range
Coarse and fine adjustment modes
Up to three clock frequency domains
Flexible clock reference and external feedback inputs with programmable single-ended or differential input reference standards (LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL), clock A/B selection multiplexer, and programmable feedback standards (LVTTL, LVCMOS, SSTL, HSTL)
Programmable termination
All inputs and outputs are hot socket compliant
Full JTAG boundary scan test and in-system programming support

Applications
Circuit board common clock distribution
PLL-based frequency generation
High fan-out clock buffer
Zero-delay clock buffer