IDT, Integrated Device Technology Inc IDT5V993A-2QG

Description
The IDT5V993A is a high fanout 3.3V PLL-based clock driver designed for high-performance computing and data-communications applications. It features programmable skew, allowing outputs to lead or lag the reference input signal. The device has six programmable skew outputs and two zero skew outputs. Skew is controlled by 3-level input signals.
When the GND/SOE pin is held low, all outputs are synchronously enabled. However, if GND/SOE is held high, all outputs except 3Q0 and 3Q1 are synchronously disabled. Additionally, when the Vcco/PE is held high, all outputs are synchronized with the positive edge of the REF clock input. When Vcco/PE is held low, all outputs are synchronized with the negative edge of REF.
The IDT5V993A has LVTTL outputs with 12mA balanced drive outputs and low jitter (<200ps peak-to-peak). It is available in a QSOP package.

Features
3.3V operation
5V tolerant reference input
3 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization
Synchronous output enable
Output frequency: 3.75MHz to 85MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
IDT5V993A-2: tSKEWO < 250ps
IDT5V993A-5: tSKEWO < 500ps
IDT5V993A-7: tSKEWO < 750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low jitter: <200ps peak-to-peak
Available in QSOP package

Applications
High-performance computing
Data communications
DSP applications
Clock distribution
Skew compensation