IDT, Integrated Device Technology Inc IDT5V991A-2JGI

Description
The IDT5V991A is a high fanout 3.3V PLL-based clock driver designed for high-performance computing and data-communications applications. It features programmable skew outputs, allowing outputs to lead or lag the REF input signal. The device has eight programmable skew outputs in four banks of two, controlled by 3-level input signals.
When the GND/SOE pin is held low, all outputs are synchronously enabled. However, if GND/SOE is held high, all outputs except 300 and 301 are synchronously disabled. Additionally, when Vcco/PE is held high, all outputs are synchronized with the positive edge of the REF clock input. When Vcco/PE is held low, all outputs are synchronized with the negative edge of REF.
The IDT5V991A has LVTTL outputs with 12mA balanced drive outputs and low jitter (<200ps peak-to-peak). It is available in a 32-pin PLCC package.

Features
REF is 5V tolerant
4 pairs of programmable skew outputs
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER
TURBOCLOCK™
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization: Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75MHz to 85MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
IDT5V991A-2: ISKEWO < 250ps
IDT5V991A-5: ISKEWO < 500ps
IDT5V991A-7: tSKEWO < 750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps peak-to-peak
Available in 32-pin PLCC Package

Applications
High-performance computing
Data-communications
DSP applications