IDT, Integrated Device Technology Inc IDT23S09E-1DCG

Description
The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer designed for high-speed clock distribution applications. It operates within a frequency range of 10 to 200MHz and aligns the phase between the incoming clock and the output clock, achieving zero delay.
The IDT23S09E accepts one reference input and drives two banks of four low skew clocks. It features on-chip PLLs that lock to the input clock on the REF pin. In the absence of an input clock, the device enters power down mode, drawing less than 12μA (Commercial Temperature range) or 25µA (Industrial temperature range) and tri-stating the outputs.

Features
Phase-Lock Loop Clock Distribution
10MHz to 200MHz operating frequency
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
Distributes one clock input to one bank of five and one bank of four outputs
Separate output enable for each output bank
Output Skew <250ps
Low jitter <200 ps cycle-to-cycle
IDT23S09E-1 for Standard Drive
IDT23S09E-1H for High Drive
No external RC network required
Operates at 3.3V VDD
Spread spectrum compatible
Available in SOIC and TSSOP packages

Applications
High-speed clock distribution
Datacom and telecom systems
Networking equipment
Industrial automation
Test and measurement equipment