Altera EPM7160ELC84-20 technical specifications, attributes, parameters and parts with similar specifications to Altera EPM7160ELC84-20.
- Mounting TypeSurface Mount
- Package / Case84-LCC (J-Lead)
- Surface MountYES
- Operating Temperature0°C~70°C TA
- PackagingTray
- Published1998
- SeriesMAX® 7000
- JESD-609 Codee0
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations84
- ECCN CodeEAR99
- Terminal FinishTIN LEAD
- Additional FeatureCONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
- HTS Code8542.39.00.01
- SubcategoryProgrammable Logic Devices
- TechnologyCMOS
- Terminal PositionQUAD
- Terminal FormJ BEND
- Peak Reflow Temperature (Cel)220
- Supply Voltage5V
- Terminal Pitch1.27mm
- Reflow Temperature-Max (s)30
- Base Part NumberEPM7160
- JESD-30 CodeS-PQCC-J84
- Qualification StatusNot Qualified
- Supply Voltage-Max (Vsup)5.25V
- Power Supplies3.3/55V
- Supply Voltage-Min (Vsup)4.75V
- Programmable TypeEE PLD
- Number of I/O64
- Clock Frequency83.3MHz
- Propagation Delay20 ns
- Number of Gates3200
- Output FunctionMACROCELL
- Number of Macro Cells160
- JTAG BSTNO
- Voltage Supply - Internal4.75V~5.25V
- Delay Time tpd(1) Max20ns
- Number of Logic Elements/Blocks10
- Height Seated (Max)5.08mm
- Length29.3116mm
- Width29.3116mm
- RoHS StatusNon-RoHS Compliant
EPM7160ELC84-20 Overview
This product has 84 terminations and falls under the EAR99 ECCN code. The terminal finish is TIN LEAD and the terminal position is QUAD. The peak reflow temperature is 220 degrees Celsius and the maximum reflow time is 30 seconds. It requires power supplies of 3.3/55V and has a total of 3200 gates. The maximum seated height is 5.08mm and the length is 29.3116mm.
EPM7160ELC84-20 Features
84-LCC (J-Lead) package
64 I/Os
The operating temperature of 0°C~70°C TA
3.3/55V power supplies
EPM7160ELC84-20 Applications
There are a lot of Intel EPM7160ELC84-20 CPLDs applications.
State machine design
PULSE WIDTH MODULATION (PWM)
USB Bus
ON-CHIP OSCILLATOR CIRCUIT
STANDARD SERIAL INTERFACE UART
Random logic replacement
Timing control
ROM patching
Power up sequencing
Power Meter SMPS
This product has 84 terminations and falls under the EAR99 ECCN code. The terminal finish is TIN LEAD and the terminal position is QUAD. The peak reflow temperature is 220 degrees Celsius and the maximum reflow time is 30 seconds. It requires power supplies of 3.3/55V and has a total of 3200 gates. The maximum seated height is 5.08mm and the length is 29.3116mm.
EPM7160ELC84-20 Features
84-LCC (J-Lead) package
64 I/Os
The operating temperature of 0°C~70°C TA
3.3/55V power supplies
EPM7160ELC84-20 Applications
There are a lot of Intel EPM7160ELC84-20 CPLDs applications.
State machine design
PULSE WIDTH MODULATION (PWM)
USB Bus
ON-CHIP OSCILLATOR CIRCUIT
STANDARD SERIAL INTERFACE UART
Random logic replacement
Timing control
ROM patching
Power up sequencing
Power Meter SMPS
EPM7160ELC84-20 More Descriptions
CPLD MAX® 7000 Family 3.2K Gates 160 Macro Cells 62.5MHz CMOS Technology 5V 84-Pin PLCC Tube
CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 160 Macro 64 IOs
MACROCELL Active Surface Mount COMMERCIAL CPLD 70C 5.25V 20ns 29.31mm
Product Description Demo for Development.
French Electronic Distributor since 1988
EE PLD, 20ns, 160-Cell, CMOS, PQCC84
E/P ENHANCED 160 M/C 84 P. PLD
CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 160 Macro 64 IOs
MACROCELL Active Surface Mount COMMERCIAL CPLD 70C 5.25V 20ns 29.31mm
Product Description Demo for Development.
French Electronic Distributor since 1988
EE PLD, 20ns, 160-Cell, CMOS, PQCC84
E/P ENHANCED 160 M/C 84 P. PLD
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