Altera EPM7128ELC84-20

Name: EPM7128ELC84-20
Brand: Altera
SKU: 3122388-EPM7128ELC84-20
Availability: InStock
Rating: 5 (1 reviews)

Part Number:: EPM7128ELC84-20

Manufacturer:: Altera

Ventron No:: 3122388-EPM7128ELC84-20

Description:: IC CPLD 128MC 20NS 84PLCC

ECAD Model:

Datasheet:: MAX 7000

Specifications

Altera EPM7128ELC84-20 technical specifications, attributes, parameters and parts with similar specifications to Altera EPM7128ELC84-20.

Mounting Type
Surface Mount
Package / Case
84-LCC (J-Lead)
Surface Mount
YES
Operating Temperature
0°C~70°C TA
Packaging
Tray
Published
1998
Series
MAX® 7000
JESD-609 Code
e0
Part Status
Obsolete
Moisture Sensitivity Level (MSL)
2 (1 Year)
Number of Terminations
84
ECCN Code
EAR99
Terminal Finish
TIN LEAD
Subcategory
Programmable Logic Devices
Technology
CMOS
Terminal Position
QUAD
Terminal Form
J BEND
Peak Reflow Temperature (Cel)
220
Supply Voltage
5V
Terminal Pitch
1.27mm
Reflow Temperature-Max (s)
30
Base Part Number
EPM7128
Qualification Status
Not Qualified
Supply Voltage-Max (Vsup)
5.25V
Power Supplies
3.3/55V
Supply Voltage-Min (Vsup)
4.75V
Programmable Type
EE PLD
Number of I/O
68
Propagation Delay
20 ns
Number of Gates
2500
Output Function
MACROCELL
Number of Macro Cells
128
JTAG BST
NO
Voltage Supply - Internal
4.75V~5.25V
Delay Time tpd(1) Max
20ns
Number of Logic Elements/Blocks
8
Length
29.3116mm
Width
29.3116mm
RoHS Status
Non-RoHS Compliant

Description

EPM7128ELC84-20 Description
The MAX® 7000 series from Altera is a line of Embedded - CPLDs (Complex Programmable Logic Devices) chips. These chips are designed with a CMOS technology and have a maximum operating temperature of 0°C to 70°C. They come in a tray packaging and have a JESD-609 Code of e0. With a surface mount option, this chip has 68 I/O pins and 2500 gates. It also has 8 logic elements/blocks and does not have a JTAG BST feature.

EPM7128ELC84-20 Features
High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells

EPM7128ELC84-20 Applications
Communications equipment Broadband fixed line access Enterprise systems Enterprise projectors Personal electronics Portable electronics

EPM7128ELC84-20 More Descriptions

CPLD MAX 7000 Family 2.5K Gates 128 Macro Cells 83.33MHz CMOS Technology 5 Volt 84-Pin PLCC
CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 128 Macro 68 IOs
LOGIC, FLIP FLOP DUAL J-K, 16DIP
Product Description Demo for Development.
French Electronic Distributor since 1988
EE PLD, 20ns, 128-Cell, CMOS, PQCC84

Certification