Maxim Integrated DS34T101GN

Description
IETF PWE3 SATOP/CESOPSN/TDMoIP/HDLC-compliant devices
Transport up to eight E1, T1, or serial streams or one high-speed E3, T3, STS-1, or serial stream over IP, MPLS, or Ethernet networks
Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications
TDM data transported in up to 64 individually configurable bundles
Support all standards-based TDM-over-packet mapping methods except AAL2
Support frame-based serial HDLC data flows
Built-in full-featured E1/T1 framers and LIUs

Features
Full-featured IC includes E1/T1 LIUs and framers, TDMOP engine, and 10/100 MAC
Transport of E1, T1, E3, T3, or STS-1 TDM or other CBR signals over packet networks
Full support for SATOP, CESOPSN, TDMoIP AAL1, HDLC, unstructured, structured, and structured with CAS mapping methods
Adaptive clock recovery, common clock, external clock, and loopback timing modes
On-chip TDM clock recovery machines, one per port, independently configurable
Clock recovery algorithm handles network PDV, packet loss, constant delay changes, frequency changes, and other impairments
64 independent bundles/connections
Multiprotocol encapsulation supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, and Metro Ethernet
VLAN support according to 802.1p and 802.1Q
10/100 Ethernet MAC supports MII/RMII/SSMI
Selectable 32-bit, 16-bit, or SPI processor bus
Operates from only two clock signals, one for clock recovery and one for packet processing
Glueless SDRAM buffer management
Low-power 1.8V core, 3.3V I/O

Applications
TDM circuit extension over PSN
Leased-line services over PSN
TDM over GPON/EPON
TDM over cable
TDM over wireless
Cellular backhaul over PSN
Multiservice over unified PSN
HDLC-based traffic transport over PSN