Cypress Semiconductor Corp CY2309SXC-1H
- Part Number:
- CY2309SXC-1H
- Manufacturer:
- Cypress Semiconductor Corp
- Ventron No:
- 2977931-CY2309SXC-1H
- Description:
- IC CLK ZDB 9OUT 133MHZ 16SOIC
- Datasheet:
- CY2309SXC-1H
Description
The CY2305/CY2309 is a low-cost, 3.3-V zero delay buffer designed to distribute high-speed clocks. It is available in 8-pin SOIC (CY2305) and 16-pin SOIC or TSSOP (CY2309) packages. The CY2305 has one input and five outputs, while the CY2309 has one input and nine outputs, grouped as 4 4 1.
The CY2305/CY2309 has an on-chip PLL that locks to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The PLLs enter a power-down mode when there are no rising edges on the REF input, resulting in less than 25.0 μA current draw.
Features
10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies
Zero input-output propagation delay
60-ps typical cycle-to-cycle jitter (high drive)
Multiple low skew outputs
85 ps typical output-to-output skew
One input drives five outputs (CY2305)
One input drives nine outputs, grouped as 4 4 1 (CY2309)
Compatible with Pentium-based systems
Test Mode to bypass phase-locked loop (PLL) (CY2309)
3.3-V operation
Commercial and industrial temperature ranges
Applications
Clock distribution in high-speed systems
PCI bus clock distribution
CPU clock distribution
Test and measurement equipment
The CY2305/CY2309 is a low-cost, 3.3-V zero delay buffer designed to distribute high-speed clocks. It is available in 8-pin SOIC (CY2305) and 16-pin SOIC or TSSOP (CY2309) packages. The CY2305 has one input and five outputs, while the CY2309 has one input and nine outputs, grouped as 4 4 1.
The CY2305/CY2309 has an on-chip PLL that locks to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The PLLs enter a power-down mode when there are no rising edges on the REF input, resulting in less than 25.0 μA current draw.
Features
10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies
Zero input-output propagation delay
60-ps typical cycle-to-cycle jitter (high drive)
Multiple low skew outputs
85 ps typical output-to-output skew
One input drives five outputs (CY2305)
One input drives nine outputs, grouped as 4 4 1 (CY2309)
Compatible with Pentium-based systems
Test Mode to bypass phase-locked loop (PLL) (CY2309)
3.3-V operation
Commercial and industrial temperature ranges
Applications
Clock distribution in high-speed systems
PCI bus clock distribution
CPU clock distribution
Test and measurement equipment
Cypress Semiconductor Corp CY2309SXC-1H technical specifications, attributes, parameters and parts with similar specifications to Cypress Semiconductor Corp CY2309SXC-1H.
- Factory Lead Time6 Weeks
- Contact PlatingGold, Tin
- Mounting TypeSurface Mount
- Package / Case16-SOIC (0.154, 3.90mm Width)
- Surface MountYES
- Number of Pins16
- Operating Temperature0°C~70°C
- PackagingTube
- Published2002
- JESD-609 Codee4
- Pbfree Codeyes
- Part StatusActive
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations16
- Terminal FinishNickel/Palladium/Gold (Ni/Pd/Au)
- SubcategoryClock Drivers
- Voltage - Supply3V~3.6V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)260
- Number of Functions1
- Supply Voltage3.3V
- Frequency133.33MHz
- Reflow Temperature-Max (s)30
- Base Part NumberCY2309
- OutputLVCMOS
- Pin Count16
- Number of Outputs9
- Operating Supply Voltage3.3V
- Supply Voltage-Max (Vsup)3.6V
- Supply Voltage-Min (Vsup)3V
- Number of Circuits1
- Nominal Supply Current32mA
- Max Supply Current32mA
- InputLVCMOS, LVTTL
- Ratio - Input:Output1:9
- Max I(ol)0.008 A
- PLLYes with Bypass
- Differential - Input:OutputNo/No
- Propagation Delay (tpd)8.7 ns
- Same Edge Skew-Max (tskwd)0.25 ns
- Height1.48mm
- Length9.98mm
- Width3.98mm
- Radiation HardeningNo
- RoHS StatusROHS3 Compliant
- Lead FreeLead Free
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