Cypress Semiconductor Corp CY2304SC-1
- Part Number:
- CY2304SC-1
- Manufacturer:
- Cypress Semiconductor Corp
- Ventron No:
- 2981778-CY2304SC-1
- Description:
- IC CLK ZDB 4OUT 133MHZ 8SOIC
- Datasheet:
- CY2304
Description
The CY2304 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. It features an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps.
The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps.
Features
Zero input-output propagation delay, adjustable by capacitive load on FBK input
Multiple configurations
Multiple low-skew outputs
10 MHz to 133 MHz operating range
90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz
Space-saving 8-pin 150-mil SOIC package
3.3V operation
Industrial temperature available
Applications
Clock distribution in PC, workstation, datacom, telecom, and other high-performance applications
High-speed clock buffering
Clock skew reduction
Clock multiplication and division
The CY2304 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. It features an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps.
The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps.
Features
Zero input-output propagation delay, adjustable by capacitive load on FBK input
Multiple configurations
Multiple low-skew outputs
10 MHz to 133 MHz operating range
90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz
Space-saving 8-pin 150-mil SOIC package
3.3V operation
Industrial temperature available
Applications
Clock distribution in PC, workstation, datacom, telecom, and other high-performance applications
High-speed clock buffering
Clock skew reduction
Clock multiplication and division
Cypress Semiconductor Corp CY2304SC-1 technical specifications, attributes, parameters and parts with similar specifications to Cypress Semiconductor Corp CY2304SC-1.
- MountSurface Mount
- Mounting TypeSurface Mount
- Package / Case8-SOIC (0.154, 3.90mm Width)
- Number of Pins8
- Operating Temperature0°C~70°C
- PackagingTube
- Published2002
- JESD-609 Codee0
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations8
- Terminal FinishTIN LEAD
- TechnologyCMOS
- Voltage - Supply3V~3.6V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)220
- Number of Functions1
- Supply Voltage3.3V
- Reach Compliance Codenot_compliant
- Reflow Temperature-Max (s)NOT SPECIFIED
- Base Part NumberCY2304
- Pin Count8
- Qualification StatusNot Qualified
- Operating Supply Voltage3.3V
- Supply Voltage-Max (Vsup)3.6V
- Supply Voltage-Min (Vsup)3V
- Number of Circuits1
- Nominal Supply Current45mA
- Frequency (Max)133.3MHz
- Output Characteristics3-STATE
- InputClock
- Ratio - Input:Output1:4
- PLLYes
- Differential - Input:OutputNo/No
- Same Edge Skew-Max (tskwd)0.2 ns
- Number of True Outputs4
- RoHS StatusNon-RoHS Compliant
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