Analog Devices Inc. AD9517-4ABCPZ

Description
The AD95174 is a multioutput clock distribution function with subpicosecond jitter performance, along with an onchip PLL and VCO. The onchip VCO tunes from 1.45 GHz to 1.80 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.
The AD95174 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

Features
Low phase noise, phaselocked loop (PLL)
Onchip VCO tunes from 1.45 GHz to 1.80 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 singleended reference inputs
Reference monitoring capability
Automatic revertive and manual reference switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
2 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1to32 divider with coarse phase delay
Additive output jitter: 225 fs rms
Channeltochannel skew paired outputs of <10 ps
2 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1to32 dividers with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (At) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz CMOS outputs
Automatic synchronization of all outputs on powerup
Manual output synchronization available
Available in a 48lead LFCSP

Applications
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation