Analog Devices Inc. AD800-52BR

Description
The AD800 and AD802 are phaselocked loop (PLL) devices that perform clock recovery and data retiming on NonReturn to Zero (NRZ) data. They support data rates between 20 Mbps and 160 Mbps and are designed for standard telecommunications bit rates:
AD80045: 44.736 Mbps (DS3)
AD80052: 51.84 Mbps (STS1)
AD802155: 155.52 Mbps (STS3 or STM1)
These devices do not require a preamble or external VCXO to lock onto input data. They use two control loops to acquire frequency and phase lock. The frequency acquisition control loop initially acquires the clock frequency of the input data, while the phaselock loop acquires the phase and ensures that the output signals track changes in the input data phase.
The loop damping is userselectable via a capacitor, which affects jitter peaking performance and acquisition time. The devices exhibit 0.08 dB jitter peaking and acquire lock on random or scrambled data within 4x10^9 bit periods with a damping factor of 5.
During acquisition, the frequency detector provides a Frequency Acquisition (FRAC) signal indicating that the device has not yet locked onto the input data. Once frequency lock is acquired, no pulses occur at the FRAC output.
The devices include a precisely trimmed VCO, eliminating the need for external components for setting center frequency and trimming. The VCO provides a clock output within ±20% of the device center frequency in the absence of input data.
The AD800 and AD802 exhibit virtually no pattern jitter due to the patented phase detector. Total loop jitter is 20° peaktopeak. Jitter bandwidth is dictated by maskprogrammable fractional loop bandwidth. The AD800 has a nominal loop bandwidth of 0.1% of the center frequency for data rates below 90 Mbps, while the AD802 has a loop bandwidth of 0.08% of center frequency for data rates above 90 Mbps.

Features
Standard products for specific telecommunications bit rates
Accepts NRZ data, no preamble required
Recovered clock and retimed data outputs
Phaselocked loop type clock recovery, no crystal required
Random jitter: 20° peaktopeak
Pattern jitter: Virtually eliminated
10 kHz ECL compatible
Single supply operation: 5.2 V or 5 V
Wide operating temperature range: 40°C to 85°C

Applications
Clock recovery and data retiming in telecommunications systems
Data synchronization and resynchronization
Jitter reduction in highspeed data transmission systems