IDT, Integrated Device Technology Inc 82V3202NLG

Description
Integrated singlechip solution for Synchronous Equipment Timing Source
Supports Stratum 3, SMC, 4E, and 4 clocks in SONET/SDH, DWDM, and wireless base stations
Supports three input clock sources: recovered clock from STMN or OCn, PDH network synchronization timing, and external synchronization reference timing
Automatic or manual input clock selection for DPLL locking
Three primary DPLL operating modes: FreeRun, Locked, and Holdover
Programmable DPLL bandwidths (0.1 Hz to 560 Hz) and damping factors (1.2 to 20)
Highstable input required for master clock, calibrated within ±741 ppm
I²C programming interface for register access
Typically used in Line Card applications

Features
Integrated solution for SONET/SDH timing
Supports multiple input clock sources
Automatic or manual input clock selection
Three DPLL operating modes
Programmable DPLL bandwidths and damping factors
Highstable master clock input
I²C programming interface

Applications
SONET/SDH equipments
DWDM
Wireless base stations (GSM, 3G, etc.)
DSL concentrators
Routers
Access Network applications