IDT, Integrated Device Technology Inc 23S09E-1HPGGI8

Description
The IDT23S09E is a highspeed phaselock loop (PLL) clock buffer designed for highspeed clock distribution applications. It operates within a frequency range of 10 to 200MHz and achieves zero delay by aligning the phase between the incoming and output clocks. The device accepts one reference input and drives two banks of four low skew clocks. It features onchip PLLs that lock to the input clock and obtain feedback from the CLKOUT pad. In the absence of an input clock, the IDT23S09E enters power down mode, drawing less than 12μA (Commercial) or 25µA (Industrial) and tristating the outputs.

Features
PhaseLock Loop Clock Distribution
10MHz to 200MHz operating frequency
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
Distributes one clock input to one bank of five and one bank of four outputs
Separate output enable for each output bank
Output Skew <250ps
Low jitter <200 ps cycletocycle
IDT23S09E1 for Standard Drive
IDT23S09E1H for High Drive
No external RC network required
Operates at 3.3V VDD
Spread spectrum compatible
Available in SOIC and TSSOP packages

Applications
Highspeed clock distribution
Networking and telecommunications
Data processing and storage
Industrial automation
Medical electronics