IDT, Integrated Device Technology Inc 23S08-1HPGG

Description
The IDT23S08 is a highspeed phaselock loop (PLL) clock multiplier designed for highspeed clock distribution and multiplication applications. It operates within a frequency range of 10 to 133MHz and achieves zero delay by aligning the phase between the incoming clock and the output clock.
The IDT23S08 has two banks of four outputs each, controlled by two select addresses. Both banks can be put into tristate mode through proper selection of input addresses. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing. In the absence of an input clock, the device enters power down mode, drawing less than 12μA (Commercial Temperature range) or 25μA (Industrial temperature range) and tristating the outputs.
The IDT23S08 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. The PLL is closed externally, providing flexibility in controlling the delay between the input clock and the outputs.

Features
3.3V zero delay clock multiplier
Spread spectrum compatible
PhaseLock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency
Distributes one clock input to two banks of four outputs
Separate output enable for each output bank
External feedback (FBK) pin synchronizes the outputs to the clock input
Output Skew <200 ps
Low jitter <200 ps cycletocycle
1x, 2x, 4x output options
No external RC network required
Operates at 3.3V VDD
Spread spectrum compatible
Available in SOIC and TSSOP packages

Applications
Highspeed clock distribution
Clock multiplication
Phaselocked loop applications
Spread spectrum applications