Microsemi Corporation ZL40250LDG1

Description
The ZL40250ZL40253 SmartBuffer™ are 6 or 10output programmable fanout buffers with multiformat logic (L) outputs. They feature four flexible input clocks, six or ten universal output clocks with dividers, and multiple output supply voltage banks with CMOS output voltages from 1.5V to 3.3V. The buffers offer low additive jitter (<200fs RMS for input frequencies ≥100MHz), precise output alignment circuitry, peroutput skew adjustment, and peroutput enable/disable and glitchless start/stop. They are ideal for clock signal fanout, format conversion, frequency division, and skew adjustment in a wide variety of equipment types.

Features
Four flexible input clocks:
One crystal/CMOS input
Two differential/CMOS inputs
One singleended/CMOS input
Any input frequency up to 1GHz (300MHz for CMOS)
Manual clock switching by pin or register
Six or ten universal output clocks with dividers:
Each output has an independent divider
Low additive jitter (<200fs RMS for input frequencies ≥100MHz)
Each output configurable as LVDS, LVPECL, HCSL, 2xCMOS, or HSTL
In 2xCMOS mode, the P and N pins can be different frequencies (e.g., 125MHz and 25MHz)
Multiple output supply voltage banks with CMOS output voltages from 1.5V to 3.3V
Precise output alignment circuitry from GPIO pin or register bit
Peroutput skew adjustment
Peroutput enable/disable and glitchless start/stop (stop high or low)
Four multipurpose I/O pins
SPI or I²C processor interface
Core supply voltage options: 2.5V only, 3.3V only, 1.8V 2.5V, or 1.8V 3.3V
Spacesaving 8x8mm QFN56 (0.5mm pitch)
Easytouse evaluation/programming software

Applications
Clock signal fanout
Format conversion
Frequency division
Skew adjustment
PCIe 1, 2, 3, 4 compliant