Microchip Technology SY89872UMG-TR

Description
2.5V, 2 GHz any differential intoLVDS programmable clock divider/fanout buffer with internal termination
Guaranteed AC performance over temperature and voltage:
>2 GHz max
<750 ps tpd (matched delay between banks)
<15 ps withindevice skew
<200 ps 1/4
Low jitter design: 265 fs RMS phase jitter
Unique input termination and VT pin for DCcoupled and ACcoupled inputs: any differential inputs (LVPECL, LVDS, CML, HTSL)
Precision differential LVDS outputs
Matched delay: all outputs have matched delay, independent of divider setting
TTL/CMOS inputs for select and reset/disable
Two output banks (matched delay):
Bank A: buffered copy of input clock (undivided)
Bank B: divided output ( 2, 4, 8, 16), two copies
2.5V power supply
Wide operating temperature range: 40°C to 85°C
Available in 3 mm × 3 mm 16lead VQFN package

Features
Guaranteed AC performance over temperature and voltage
Low jitter design
Unique input termination and VT pin for DCcoupled and ACcoupled inputs
Precision differential LVDS outputs
Matched delay: all outputs have matched delay, independent of divider setting
TTL/CMOS inputs for select and reset/disable
Two output banks (matched delay)
2.5V power supply
Wide operating temperature range
Available in 3 mm × 3 mm 16lead VQFN package

Applications
OC3 to OC192 SONET/SDH applications
Transponders
Oscillators
SONET/SDH line cards