Microchip Technology SY89823LHI

Description
The SY89823L is a highperformance bus clock driver with 22 differential HighSpeed Transceiver Logic (HSTL), 1.5V compatible output pairs. It is designed for lowvoltage (3.3V/1.8V) applications requiring a large number of outputs to drive precisely aligned, ultralow skew signals. The input is multiplexed from either HSTL or LowVoltage PositiveEmitterCoupled Logic (LVPECL) by the CLK_SEL pin.
The Output Enable (OE) is synchronous and triplebuffered, ensuring that the outputs are only enabled/disabled when they are already in the LOW state. This avoids potential runt clock pulses during enable/disable transitions. The triplebuffering feature provides a threeclock delay from the time the OE input is asserted/deasserted to when the clock appears at the outputs.
The SY89823L features low pintopin skew (50ps max.) and low parttopart skew (200ps max.), previously unachievable in a standard product with such a high number of outputs. It is available in a single, spacesaving package, enabling a lower overall cost solution.

Features
22 differential HSTL (lowvoltage swing) output pairs
HSTL outputs drive 50Ω to ground with no offset voltage
3.3V core supply, 1.8V output supply for reduced power
LVPECL and HSTL inputs
Low parttopart skew (200ps max.)
Low pintopin skew (50ps max.)
Triplebuffered output enable (OE)
40°C to 85°C temperature range
Available in a 64pin EPADTQFP

Applications
Highperformance PCs
Workstations
Parallel processorbased systems
Other highperformance computing
Communications