Microchip Technology SY89112UMG

Description
The SY89112U is a low jitter, low skew, highspeed LVPECL 1:12 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. It features a 2:1 input MUX for clock switchover and a unique isolation design to minimize channeltochannel crosstalk. The SY89112U distributes clock frequencies from DC to >2GHz guaranteed over temperature and voltage. It incorporates a synchronous output enable (EN) to prevent "runt" clock pulses. The differential input includes a 3pin input termination architecture that directly interfaces to any differential signal (AC or DCcoupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks. For ACcoupled input interface, an onboard output reference voltage (VREFAC) is provided to bias the centertap (VT) pin. The outputs are 800mV, 100Kcompatible LVPECL with fast rise/fall times guaranteed to be less than 220ps. The SY89112U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of 40°C to 85°C.

Features
Precision Edge®
Selects between 1 of 2 inputs and provides 12 precision, low skew LVPECL output copies
Guaranteed AC performance over temperature and voltage:
DC to >2GHz throughput
<550ps propagation delay CLKtoQ
<220ps rise/fall time
<25ps outputtooutput skew
Ultralow jitter design:
<1ps) random jitter
<10ps total jitter (clock)
<1ps(ms) cycletocycle jitter
<0.7psma crosstalk induced jitter
Unique, patentpending input termination and VT pin accepts DCcoupled and ACcoupled differential inputs
Unique, patentpending 2:1 input MUX provides superior isolation to minimize channeltochannel crosstalk
800mV, 100K LVPECL output swing
Power supply 2.5V 5% or 3.3V 10%
Industrial temperature range 40°C to 85°C
Available in 44pin (7mm x 7mm) MLF™ package

Applications
Multiprocessor server
SONET/SDH clock/data distribution
Fibre Channel distribution
Gigabit Ethernet clock distribution