Microchip Technology SY100EL34LZG-TR

Description
The SY10/100EL34/L are low-skew 2, 4, 8 clock generation chips designed for low-skew clock generation applications. The internal dividers are synchronous to each other, resulting in precisely aligned common output edges. The devices can be driven by differential or single-ended ECL or PECL input signals. The VBB output allows for AC-coupling of a sinusoidal source into the device. The V output acts as the switching reference for the input of the EL34/L under single-ended input conditions, with a current sourcing/sinking capacity of up to 0.5mA.
The synchronous enable/disable feature ensures that the internal dividers are only enabled/disabled when the internal clock is in the LOW state, preventing runt clock pulses. The internal enable flip-flop is clocked on the falling edge of the input clock, and all specification limits are referenced to the negative edge of the clock input.
Upon start-up, the internal flip-flops attain a random state. The master reset (MR) input allows for synchronization of the internal dividers and multiple EL34/Ls in a system.

Features
3.3V and 5V power supply options
50ps output-to-output skew
Synchronous enable/disable
Master reset for synchronization
Internal 75KQ input pull-down resistors
Available in 16-pin SOIC package

Applications
Clock generation for high-speed digital systems
Synchronization of multiple devices
Data communication systems
Test and measurement equipment