SN74ACT7807-40FN

Texas Instruments SN74ACT7807-40FN

Part Number:
SN74ACT7807-40FN
Manufacturer:
Texas Instruments
Ventron No:
3210370-SN74ACT7807-40FN
Description:
IC SYNC FIFO MEM 2048X9 44-PLCC
ECAD Model:
Datasheet:
SN74ACT7807

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Specifications
Texas Instruments SN74ACT7807-40FN technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74ACT7807-40FN.
  • Mounting Type
    Surface Mount
  • Package / Case
    44-LCC (J-Lead)
  • Surface Mount
    YES
  • Operating Temperature
    0°C~70°C
  • Packaging
    Tube
  • Series
    74ACT
  • JESD-609 Code
    e4
  • Pbfree Code
    yes
  • Part Status
    Obsolete
  • Moisture Sensitivity Level (MSL)
    3 (168 Hours)
  • Number of Terminations
    44
  • Terminal Finish
    NICKEL PALLADIUM GOLD
  • Technology
    CMOS
  • Voltage - Supply
    4.5V~5.5V
  • Terminal Position
    QUAD
  • Terminal Form
    J BEND
  • Peak Reflow Temperature (Cel)
    260
  • Supply Voltage
    5V
  • Terminal Pitch
    1.27mm
  • JESD-30 Code
    S-PQCC-J44
  • Function
    Synchronous
  • Current - Supply (Max)
    400μA
  • Qualification Status
    COMMERCIAL
  • Supply Voltage-Max (Vsup)
    5.5V
  • Supply Voltage-Min (Vsup)
    4.5V
  • Memory Size
    18K 2K x 9
  • Access Time
    25ns
  • Data Rate
    25MHz
  • Organization
    2KX9
  • Memory Width
    9
  • Memory Density
    18432 bit
  • Parallel/Serial
    PARALLEL
  • Bus Directional
    Uni-Directional
  • Retransmit Capability
    No
  • Programmable Flags Support
    Yes
  • Output Enable
    YES
  • Expansion Type
    Depth, Width
  • Cycle Time
    40 ns
  • Height Seated (Max)
    4.57mm
  • Length
    16.585mm
  • Width
    16.585mm
  • RoHS Status
    ROHS3 Compliant
Description
SN74ACT7807-40FN Overview
The package or case of the device is 44-LCC (J-Lead), which refers to the specific type of packaging used. It has a total of 44 terminations, indicating the number of connection points on the device. The supply voltage required for this device is 5V, which is the electrical power needed to operate it. The memory size is 18K 2K x 9, meaning it has a capacity of 18 kilobits and is organized in a 2K by 9 configuration. The memory width is 9, indicating the number of bits that can be accessed simultaneously. With a memory density of 18432 bits, it can store a significant amount of data. The bus is unidirectional, meaning data can only flow in one direction. It does not have retransmit capability, implying that it cannot resend data in case of transmission errors. The device supports programmable flags, allowing for customization and control. Lastly, the expansion type is depth and width, suggesting that the device can be expanded both in terms of capacity and accessibility.

SN74ACT7807-40FN Features
18K 2K x 9 memory size
74ACT series

SN74ACT7807-40FN Applications
There are a lot of Rochester Electronics, LLC SN74ACT7807-40FN FIFOs Memory applications.

Analog-to-digital converters
Seismic Data Collection at Extreme Temperatures
Disk Controllers
Measurement Equipment
Network bridges
Game Controller
Smart Meter
Telecommunication
Laser Receiver System
Temporary storage elements
SN74ACT7807-40FN More Descriptions
74ACT7807 Depth Width Tube 74ACT fifo memory 25MHz 400muA 16.585mm 40ns
IC SYNC FIFO MEM 2048X9 44-PLCC
The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9, WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7807 is characterized for operation from 0C to 70C.
Certification
  • ISO 9001
  • ISO 13485
  • ISO 45001
  • ASA
  • ESD
  • DUNS
  • SMTA
  • ROHS

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