Texas Instruments SN74ACT7805-40DLR

FIFO Mem Sync Dual Width Uni-Dir 256 x 18 56-Pin SSOP T/R
74ACT7805 Width Tape & Reel (TR) 8542.32.00.71 fifo memory 25MHz 400muA 0.635mm 40ns
IC FIFO SYNC 256X18 20NS 56SSOP
IC CLOCKED FIFO 256X18 56-SSOP
IC PWR SWITCH N-CHANNEL 1:1 DPAK
256 X 18 OTHER FIFO 20 ns PDSO56
FIFO, 256X18, 20NS, SYNCHRONOUS
The SN74ACT7805 is a 256-word 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0C to 70C.