Silicon Labs SL2309ZC-1T

Description
The SL2309 is a low skew, low jitter, and low power ZeroDelay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock for highspeed clock distribution applications. It features an onchip PLL that locks to the input clock at CLKIN and receives feedback internally from the CLKOUT pin. The SL2309 has two (2) clock driver banks, each with four (4) clock outputs, controlled by two (2) select input pins (S1 and S2). When only four (4) outputs are needed, four (4) bankB output clock buffers can be tristated to reduce power dissipation and jitter. The select inputs can also be used to tristate both banks A and B or drive them directly from the input, bypassing the PLL and making the product behave like a NonZero Delay Fanout Buffer (NZDB).

Features
10 to 140 MHz operating frequency range
Low output clock jitter: 140 psmax cycletocycle jitter
Low outputtooutput skew: 150 psmax
Low producttoproduct skew: 400 psmax
3.3 V power supply range
Low power dissipation: 26 mAmax at 66 MHz, 44 mAmax at 133 MHz
One input drives 9 outputs organized as 4 4 1
Select mode to bypass PLL or tristate outputs
SpreadThru™ PLL that allows use of SSCG
Standard and HighDrive options
Available in 16pin SOIC and TSSOP packages
Available in Commercial and Industrial grades

Applications
Printers and MFPs
Digital Copiers
PCs and Work Stations
DTV
Routers, Switchers, and Servers
Digital Embedded Systems