Silicon Labs SI5367C-C-GQR

Description
The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. It accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common source. The Si5367 input clock frequency and clock multiplication ratio are programmable through an I²C or SPI interface. It is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.5 V supply, the Si5367 is ideal for providing clock multiplication in high-performance timing applications.

Features
Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 10 to 710 MHz
Low jitter clock outputs with jitter generation as low as 0.6 ps rms (50 kHz-80 MHz)
Integrated loop filter with selectable loop bandwidth (150 kHz to 1.3 MHz)
Four clock inputs with manual or automatically controlled switching
Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236)
LOS alarm outputs
I²C or SPI programmable settings
On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10%, or 3.5 V ±10% operation
Small size: 14 x 14 mm 100-pin TQFP
Pb-free, RoHS compliant

Applications
SONET/SDH OC-48/OC-192 STM-16/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G709 and custom FEC line cards
Wireless base stations
Data converter clocking
XDSL
SONET/SDH PDH clock synthesis
Test and measurement