ON Semiconductor NB3N1200KMNG

Description
The NB3N1200K and NB3W1200L differential clock buffers are DB1200Z and DB1200ZL compliant and are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point-to-point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz frequency operation. The NB3N1200K and NB3W1200L utilize pseudo-external feedback topology to achieve low input-to-output delay variation. The NB3N1200K is configured with the HCSL buffer type, while the NB3W1200L is configured with the low-power NMOS Push-Pull buffer type.

Features
12 Differential Clock Output Pairs @ 0.7 V
HCSL Compatible Outputs for NB3N1200K
Low-Power NMOS Push-Pull Compatible Outputs for NB3W1200L
Optimized 100 MHz and 133 MHz Operating Frequencies to Meet The Next Generation PCIe Gen 2/Gen 3 and Intel QPI Phase Jitter
DB1200Z and DB1200ZL Compliant
3.3 V ±5% Supply Voltage Operation
Fixed-Feedback for Lowest Input-To-Output Delay Variation
SMBus Programmable Configurations to Allow Multiple Buffers in a Single Control Network
PLL Bypass Configurable for PLL or Fanout Operation
Programmable PLL. Bandwidth
2 Tri-level Addresses Selection (9 SMBUS Addresses)
Individual OE Control Pin for Each of 12 Outputs
Low Phase Jitter (Intel QPL, PCIe Gen 2/Gen 3 Phase Jitter Compliant)
50 ps Max Output-to-Output Skew Performance
50 ps Max Cycle-to-Cycle Jitter (PLL mode)
100 ps Input to Output Delay Variation Performance
QFN 64-pin Package, 9 mm x 9 mm
Spread Spectrum Compatible: Tracks Input Clock Spreading for Low EMI
0°C to 70°C Ambient Operating Temperature
These Devices are Pb-Free and are RoHS Compliant

Applications
PCIe Gen 2/Gen 3
Intel QPI
SAS
SATA
Intel SMI