ON Semiconductor NB3N106KMNG

Description
Differential 1:6 Clock fanout buffer with Highspeed Current Steering Logic (HCSL) outputs
Optimized for ultralow propagation delay variation
Designed for HCSL PCI Express clock distribution and FBDIMM applications
Inputs accept differential LVPECL, LVDS, and HCSL signals
Singleended LVPECL, HCSL, LVCMOS, or LVTTL levels accepted with external Vth reference supply
Internal 50 Ω termination resistors on input pins
Output drive current set by connecting a 475 Ω resistor from IREF to GND
Outputs can interface to LVDS receivers when terminated

Features
Typical input clock frequency: 100, 133, 166, 200, 266, 333, and 400 MHz
Typical rise and fall times: 220 ps
Typical propagation delay: 800 ps
Maximum propagation delay variation per diff pair: 100 ps
Typical integrated phase jitter RMS: 0.1 ps
Operating range: Vcc 3.0 V to 3.6 V with VEE = 0 V
Typical HCSL output levels (700 mV PeaktoPeak)
LVDS output levels with interface termination

Applications
Clock distribution
PCIe, II, III
Networking and communications
Highend computing
Servers
FBDIMM memory cards
Ethernet switch/routers