ON Semiconductor NB3F8L3005CMNTXG

Description
The NB3F8L3005C is a 2:1:5 Clock/Data fanout buffer operating on a 3.3 V / 2.5 V Core Vpp and two flexible 3.3 V/2.5 V/ 1.8 V /1.5 V VDDO, supplies which must be equal or less than VDD. A Mux selects between a Crystal input, or a differential/SE Clock/Data inputs. Differential Inputs accept LVPECL, LVDS, HCSL, or SSTL and SingleEnded levels. The MUX control line, SEL selects CLK/CLK, or Crystal input pins per Table 3. The Crystal input is disabled when a Clock input is selected. Output enable pin, OE. synchronously forces a High Impedance state (HiZ) when Low per Table 4. Outputs consist of five singleended LVCMOS outputs.

Features
Five LVCMOS /LVTTL Outputs up to 200 MHz
Differential Inputs Accept LVPECL, LVDS, HCSL, SSTL, or LVCMOS/LVTTL
Crystal Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @156.25 MHz. (12 kHz 20 MHz): 0.03 ps (Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
Single 3.3 V±5%
Single 2.5 V±5%
Mixed 3.3 V ±5% Core/2.5 V ±5% Output Operating Supply
Mixed 3.3 V ±5% Core/1.8 V±0.2 V Output Operating Supply
Mixed 3.3 V ±5% Core/1.5 V ±0.15 V Output Operating Supply
Mixed 2.5 V ±5% Core/ 1.8 V±0.2 V Output Operating Supply
Mixed 2.5 V ± 5% Core /1.5 V±0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial Temperature Range: 40°C to 85°C
These are PbFree Devices

Applications
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure

End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement