Micron Technology Inc. MT9HTF12872KY-53ED1

Mod DDR2 Sdram 1GB 244MINIRDIMM
MODULE DDR2 SDRAM 1GB 244MRDIMM
The MT9HVF3272(P)K, MT9HVF6472(P)K, and MT9HVF12872(P)K DDR2 SDRAM mod-ules are high-speed, CMOS, dynamic random-access 256MB, 512MB, and 1GB memory modules organized in x72 configuration. DDR2 SDRAM modules use internally con fig-ured quad-bank DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-tion. The double data rate architecture is essentially a 4 n-pref etch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during Writ Es. DQS is edge-aligned with data for READs and center-aligned with data for Writ Es. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR2 SDRAM modules are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting column location for the burst access. DDR2 SDRAM modules provide for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM devices support interrupting a burst read of eight with another read, or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multi bank architecture of DDR2 SDRAM devices allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible. PLL and Register Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and re drives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and clock loading. Registered mode will add one clock cycle to CL. PDF: 09005aef81c9620b/Source: 09005aef81c961ec Micron Technology, Inc. reserves the right to change products or specifications without notice.HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN 12 (C)2004, 2005 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMMSerial Presence-Detect Operation Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the Dim M's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect.