IDT, Integrated Device Technology Inc MK2302S-01LFTR

Description
The MK230201 is a highperformance Zero Delay Buffer (ZDB) that utilizes IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. It is part of IDT's ClockBlocks family and offers improved performance for higher speed and lower voltage requirements. The zero delay feature aligns the rising edge of the input clock with the rising edges of both output clocks, eliminating any perceived delay through the device. It features two outputs, one being a lowskew dividebytwo of the other output.

Features
8pin SOIC package
Pb (lead) free package (MK230201)
Low input to output skew (250 ps max)
Absolute jitter: ±500 ps
Propagation delay: 350 ps
Multiplier options: 0.5X to 16X
Output clock frequency: Up to 168 MHz at 3.3 V
Recovers degraded input clock duty cycle
Output clock duty cycle: 45/55
Full CMOS clock swings with 25 mA drive capability at TTL levels
Advanced, lowpower CMOS process
Operating voltage: 3.3 V or 5 V
Industrial temperature version available

Applications
The MK230201 is ideal for synchronizing outputs in various systems, including:
Personal computers
Data communications
Graphics/video
Offchip feedback paths to eliminate delay through other devices