ON Semiconductor MC10E431FNG

MC10E431 Series 1.1 GHz 5.7 V SMT ECL 3-Bit Differential Flip-Flop - PLCC-28
D-Type Flip Flop, 0.6Ns, Plcc-28; Logic Family/Base Number:-; Flip-Flop Type:D; Propagation Delay:600Ps; Frequency:1.1Ghz; Output Current:50Ma; Logic Case Style:Lcc; No. Of Pins:28Pins; Trigger Type:Positive Edge; Product Range:- Rohs Compliant: Yes |Onsemi MC10E431FNG
The MC10E/100E431 is a 3-bit flip-flop with differential clock data input and data output. The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset). The E431 is also designed with larger internal swings an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below VCC. The 100 Series contains temperature compensation. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open.