ON Semiconductor MC100LVEP14DTG

Description
The MC100LVEP14 is a low skew 1to5 differential driver designed for clock distribution. It accepts two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or singleended. HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
The LVEP14 guarantees low outputtooutput skew. Optimal design, layout, and processing minimize skew within a device and from device to device.
To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 ohms even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.
The MC100LVEP14 can be operated from a positive Vcc supply in PECL mode. This allows the LVEP14 to be used for high performance clock distribution in 3.3 V or 2.5 V systems. Singleended CLK input pin operation is limited to a Vcc ≤ 3.0 V in PECL mode, or VEE ≤ 3.0 V in NECL mode.

Features
100 ps DevicetoDevice Skew
25 ps Within Device Skew
400 ps Typical Propagation Delay
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode: Vcc 2.375 V to 3.8 V with VEE = 0 V
NECL Mode: Vec 0 V with V2.375 V to 3.8 V
LVDS Input Compatible
Open Input Default State
PbFree Packages are Available

Applications
Clock distribution in backplanes and boards
Highspeed data transmission
Telecommunications
Networking
Test and measurement