ON Semiconductor MC100LVE310FNR2G

Description
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed for clock distribution. It features fully differential clock paths to minimize device and system skew. The LVE310 offers two selectable clock inputs for redundant or test clocks.
To meet the tight skew specification, both sides of the differential output must be terminated into 50 ohms, even if only one side is used. In most applications, all eight differential pairs will be used and terminated. If fewer than eight pairs are used, terminate at least the output pairs adjacent to the output pair being used to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 1020 ps) of the outputs being used, which can increase skew.
The MC100LVE310 can be operated from a positive Vcc supply in LVPECL mode, allowing it to be used for highperformance clock distribution in 3.3 V systems. Designers can use the LVE310's performance to distribute low skew clocks across the backplane or the board.
The VBB pin, an internally generated voltage supply, is available to this device only. For singleended input conditions, the unused differential input is connected to Vgg as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and Vcc via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

Features
200 ps ParttoPart Skew
50 ps OutputtoOutput Skew
PECL Mode Operating Range: Vcc 3.0 V to 3.8 V with VER = 0 V
NECL Mode Operating Range: Vcc = 0 V with VEE = 3.0 V to 3.8 V
Q Output will Default LOW with All Inputs Open or at VEE
The 100 Series Contains Temperature Compensation
These Devices are PbFree, Halogen Free, and are RoHS Compliant

Applications
Clock Distribution in 3.3 V Systems
Backplane and BoardLevel Clock Distribution
HighPerformance Clocking Applications